A processor generally includes several processing units operating in parallel. Processing units conventionally include an arithmetic and logic module, an addressing module and a branch-handling module. In addition to the processing units, the processor generally includes a central unit (control unit), which communicates with the program memory and issues individual instructions, also widely called micro-instructions, to the various processing units.
Among the instructions issued to the processing units, instructions called “branching instructions” are issued to the module or to the unit handling branching. A branching instruction is an instruction implying a break in sequence in the normal sequencing of the instructions. In other words, as is conventional, a program counter is configured to issue successive values corresponding to consecutive addresses in the program memory, a branching instruction will have the effect of modifying the current value of the program counter, at a given instant and in such a way, as to force the address pointer to a given address of the program memory. Furthermore, the branching instructions can be conditional, for example guarded, as will be explained below.
All the branching instructions need to reach the branching unit before actually being processed. However, the branching unit is generally “at the bottom” of the pipelined architecture of the processor. This implies a relatively substantial latency time before a branching instruction is actually processed.